Lìrida Naviner
Professor
lirida.naviner@telecom-paristech.fr
Lìrida Naviner, Chevalier des Palmes Académiques, IEEE Senior Member and Professor at Télécom Paris. She conducts her research on the scientific challenges of IoT for the electronics industry.
https://lnaviner.wp.imt.fr/
工作经历
- 2009-至今，Full Professor,，Institut Mines-Telecom, Télécom ParisTech/CNRS-LTCI, Department Communications and Electronics, Paris, France
- 1998-2009，Maître de Conférences,，Institut Mines-Telecom, Télécom ParisTech/CNRS-LTCI, Department Communications and Electronics, Paris, France.
- 1996-1997，Professora Pesquisadora,，Federal University of Campina Grande, Computer Science Department, Campina Grande, Brazil.
- 1994-1996，Professora Pesquisadora,，Federal University of Campina Grande, Electrical Engineering Department, Campina Grande, Brazil.
研究方向
- General theme : Design of optimized digital architectures. Current themes : Reliability analysis methods & tools. Defect and fault tolerant circuits. Emerging architecture based on hybrid magnetic/CMOS devices.
论文信息
- Denis Teixeira Franco, Jean-François Naviner, and Lirida Alves de Barros Naviner. Yield and reliability issues in nanoelectronics technologies. Annals of Telecommunications, 61(11–12) :1247–1282, December 2006.
- Ali Beydoun, Van-Tam Nguyen, Lirida Alves de Barros Naviner, and Patrick Loumeau. Optimal digital reconstruction and calibration for multichannel time interleaved sigma delta adc based on comb-filters. AEU-International Journal of Electronics and Communications,67(4) :329–339, April 2013.
- Samuel Nascimento Pagliarini, Gutemberg Gonçalves dos Santos Jr, Lirida Alves de Barros Naviner, and Jean-François Naviner. Exploring the feasibility of selective hardening for combinational logic. Microelectronics Reliability Journal, 52(9-11), September 2012.
- Tian Ban and Lirida Alves de Barros Naviner. Progressive module redundancy for fault-tolerant designs in nanoelectronics. Microelectronics Reliability Journal, 51, September 2011.
- Lirida Alves de Barros Naviner, Jean-François Naviner, Gutemberg Gonçalves dos Santos Junior, Elaine Crespo Marques, and Nilson Maciel Paiva Junior. FIFA : A fault-injection fault-analysis-based tool for reliability assessment at RTL level. Microelectronics Reliability Journal, 51, September 2011.
- Gutemberg Gonçalves dos Santos Junior, Elaine Crespo Marques, Lirida Alves de Barros Naviner, and Jean-François Naviner. Using error tolerance of target application for efficient reliability improvement of digital circuits. Microelectronics Reliability Journal, 50(9-11) :1219–1222, September 2010.
- Elaine Crespo Marques, Lirida Alves de Barros Naviner, and Jean-François Naviner. An efficient tool for reliability improvement based on tmr. Microelectronics Reliability Journal,50(9-11) :1247–1250, September 2010.
- Josep Torras Flaquer, Jean-Marc Daveau, Lirida Alves de Barros Naviner, and Philippe Roche. Fast reliability analysis of combinatorial logic circuits using conditional probabilities.Microelectronics Reliability Journal, 50(9-11) :1215–1218, September 2010.
- Denis Teixeira Franco, Lirida Alves de Barros Naviner, and Jean-François Naviner. Signal probability for reliability evaluation of logic circuits. Microelectronics Reliability Journal,48 :1586–1591, September 2008.
- Mai Vasconcelos, Denis Teixeira Franco, Lirida Alves de Barros Naviner, and Jean-François Naviner. Relevant metrics for evaluation of concurrent error detection schemes. Microelec tronics Reliability Journal, 48 :1601–1603, September 2008.
- Samuel Nascimento Pagliarini, Arwa Ben Dhia, Lirida Alves de Barros Naviner, and JeanFrançois Naviner. SNAP : A novel hybrid method for circuit reliability assessment under multiple faults. Microelectronics Reliability Journal, 53(9-11), September 2013.
- Ioannis Krikidis, Jean-Luc Danger, and Lirida Naviner. An iterative reconfigurability approach for WCDMA high-data-rate communications. IEEE Wireless Communications Magazine,13(3) :8–14, June 2006.
- Leocarlos Bezerra de Lima, Francisco Marcos de Assis, and Lirida Alves de Barros Naviner.Architecture for Decoding Hermitien Codes Based on Key Equation. Journal of Communications and Information Systems, 21(1) :1–14, April 2006.
- Ioannis Krikidis, Jean-Luc Danger, and Lirida Naviner. Flexible and reconfigurable receiver architecture for WCDMA systems with low spreading factors. IEE Electronics Letters,41(1) :22–24, January 2005.
- Leocarlos Bezerra de Lima, Francisco Marcos de Assis, and Lirida Alves de Barros Naviner.Decodificaçao de codigos algébricos geométricos. Revista Brasileira de Telecomunicaçoes,18(3) :249–262, December 2003.
- Adel Ghazel, Lirida Naviner, and Khaled Grati. Design of down-sampling processors for radio communications. Analog Integrated Circuits and Signal Processing, 36(1-2) :31–38,July 2003.
- Lirida Alves de Barros Naviner and Zouhair Belkoura. Analysis of a decoding approach for Goppa codes. World Scientific and Engineering Academy and Society Transactions on Systems, 2(2) :413–416, April 2003.
- Adel Ghazel, Lirida Naviner, and Khaled Grati. On design and implementation of a decimation filter for multistandards wireless tranceivers. IEEE Transactions on Wireless Communications,1(4) :558–562, October 2002.
- Patrick Loumeau, Jean-François Naviner, Hervé Petit, Lirida Naviner, and Patricia Desgreys.Analog to digital conversion : Technical aspects. Annals of Telecommunications, 57(5-6) :413–416, May 2002.
- Elmar Melcher, Joao Marques de Carvalho, and Lirida Alves de Barros Naviner. A CMOS inverter model and extraction of reliable extended cell timing analysis. Journal of the Brazilian Computer Society, 57(5-6) :413–416, May 1995.
- Hao Cai, You Wang, Lirida Alves de Barros Naviner, and Weisheng Zhao. Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28nm FDSOI technology.Microelectronics Reliability Journal, October 2015.
- Mariem Slimani, Paulo Butzen, Lirida Naviner, You Wang, and Hao Cai. Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/cmos majority voters. Microelectronics Reliability Journal, October 2016.
- Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, and JeanFrançois Naviner. Efficient reliability evaluation methodologies for combinational circuits. Microelectronics Reliability Journal, October 2016.
- Hao Cai, You Wang, Lirida Alves de Barros Naviner, and Weisheng Zhao. Breakdown analysis of magnetic flip-flop with 28nm UTBB FDSOI technology. IEEE Transactions on Devices and Materials Reliability, 16(3) :376–383, September 2016.
- Hao Cai, You Wang, Lirida Alves de Barros Naviner, and Weisheng Zhao. Low power magnetic flip-flop optimization with FD-SOI technology boost. IEEE Transactions on Magnetics,52(8), August 2016.
- You Wang, Hao Cai, Lirida Alves de Barros Naviner, Yue Zhang, Xiaoxuan Zhao, Erya Deng, Jacques-Olivier Klein, and Weisheng Zhao. Compact model of dielectric breakdown in spin transfer torque magnetic tunnel junction. IEEE Transactions on Electronic Devices,63(4) :1762–1767, April 2016.
- Francisco Veirano, Fernando Silveira, and Lirida Naviner. Minimum operating voltage due to intrinsic noise in subthreshold digital logic in nanoscale cmos. Journal of Low Power Electronics (JOLPE), 12(1) :74–81, March 2016.
- Weisheng Zhao, Xiaoxuan Zhao, You Wang, Mengxing Wang, Shouzhong Peng, ZhangBoyu, Kaihua Cao, Lezhi Wang, Qian Shi, Wang Kang, Yu Zhang, Jacques-Olivier Klein,Lirida Alves de Barros Naviner, and Dafine Ravelosonan. Failure analysis in magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy. Materials Science Journal, 9(41) :1–17, January 2016.
- Cyril Bottoni, M. Glorieux, Jean-Marc Daveau, Gilles Gasiot, F. Abouzeid, S. Clerc, Lirida Naviner, and Philippe Roche. Soft-error-rate analysis of a sparc v8 microprocessor by fault injection over a wide range of workloads. IEEE Transactions on Reliability Journal, December2015.
- You Wang, Hao Cai, Lirida Alves de Barros Naviner, Y. Zhang, Jacques-Olivier Klein, and Weisheng Zhao. Compact thermal modeling of spin transfer torque magnetic tunnel junction.Microelectronics Reliability Journal, October 2015.
- You Wang, Hao Cai, Lirida Alves de Barros Naviner, Xiaoxuan Zhao, Yu Zhang, Mariem Slimani, Jacques-Olivier Klein, and Weisheng Zhao. A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28nm fdsoi. Microelectronics Reliability Journal, October 2016.
- Mariem Slimani, Arwa Ben Dhia, and Lirida Naviner. A novel analytical method for defect tolerance assessment. Microelectronics Reliability Journal, 55(9-10) :1285–1289, Octobre2015.
- Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, and Jean François Naviner. Cross-layer investigation of continuous-time sigma–delta modulator underaging effects. Microelectronics Reliability Journal, October 2015.
- Hao Cai, You Wang, Weisheng Zhao, and Lirida Alves de Barros Naviner. Multiplexing sense-amplifier-based magnetic flip-flop in a 28-nm FDSOI technology. IEEE Transactions on Nanotechnologies, 14(4) :761–767, July 2015.
- Arwa Ben Dhia, Mariem Slimani, Hao Cai, and Lirida Alves de Barros Naviner. A dual-rail compact defect-tolerant multiplexe. Microelectronics Reliability Journal, 55 :662–670, March 2015.
- Ting An, Kaikai Liu, Hao Cai, and Lirida Alves de Barros Naviner. Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method. Microelectronics Reliability Journal, January 2015.
- Paulo Butzen, Mariem Slimani, You Wang, Hao Cai, and Lirida Alves de Barros Naviner.Reliable majority voter based on spin transfer torque magnetic tunnel junction device. IEEE Electronics Letters, 52(1) :47–49, January 2016.
- You Wang, Y. Zhang, E.Y. Deng, Jacques-Olivier Klein, Lirida Alves de Barros Naviner, and Zhao Weisheng. Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses. Microelectronics Reliability Journal, 54(9-11) :1774–1778, 2014.
- Arwa Ben Dhia, Samuel Nascimento Pagliarini, Lirida Alves de Barros Naviner, Habib Mehrez, and Philippe Matherat. A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. Microelectronics Reliability Journal, 9-11(53), September 2013.
专利著作
- Xavier Pons Masbernart, Christophe Gruet, Eric Georgeaux, and Lirida Naviner. Battery share algorithm to reduce the energy during scanning procedures, 2016.
- Samuel Nascimento Pagliarini, Lirida Alves de Barros Naviner, and Jean-François Naviner. Estimation of the reliability of a logic circuit, September 18 2014. WO Patent App. PCT/EP2014/054,930.
- Christophe Gruet, Éric Georgeaux, Hervé Gromat, Xavier Pons Masbernat, and Lirida Naviner. Procede permettant d’etablir une strategie d’economie d’energie de batterie de terminaux mobiles, June 26 2014. WO Patent App. PCT/EP2013/003,489.
- Gutemberg Gonçalves dos Santos Jr, Lirida Naviner, Bastien Cousin, Gilles Deleuze, and Laurent Crétinon. Procédé de durcissement logique par partitionnement d’un circuit électronique, June 5 2014. WO Patent App. PCT/EP2013/075,099
- Josep Torras Flaquer, Jean-Marc Daveau, Lirida Naviner, and Philippe Roche. Method for estimating the reliability of an electronic circuit, corresponding computerized system and computer program product, October 6 2011. US Patent App. 13/074,204.
- Denis Teixeira Franco, Lirida Alves de Barros Naviner, and Jean-François Naviner. Evaluation de la fiabilité du signal des circuits numériques combinatoires., November 2008. IDDN FR.001.450011.000.S.P.2008.000.20700.
获奖信息
- IEEE Senior Member
- 2008 Chevalier de l’Ordre des Palmes Académiques